Synchronous communications are widely used in telecommunications and other serial data applications. With the advent of teleconferencing and other multimedia applications, transmission and receipt of various data types at differing rates of speed are not so easily and efficiently handled by traditional synchronous communication devices, such as modems, which are most adept at handling transmission of serial data at a given rate of speed. For instance, multimedia applications such as teleconferences may simultaneously transmit various types of data, such as radio, audio, and video, at different rates of speed.
Asynchronous transfer mode (ATM) is often used in high speed serial data communications of approximately 100 MHz with an external clock input rate of also around approximately 100 MHz to achieve simultaneous transmission of various types of data at various rates of speed. Input serial data which is synchronous (clocked) may be stored in a handshake FIFO (First In First Out), which is capable of receiving data at one rate of speed and transmitting that data at a different rate of speed, for later transmission as an ATM frame. A handshake FIFO is needed with an ATM format because transmission of serial data may occur at any frequency. Mapping a serial data frame into an ATM frame provides the advantages of a lower overhead, an asynchronous data transfer, and a faster and more interactive operation than traditional synchronous devices such as the modem. Using ATM, for instance, a given serial data application may map an E4 frame or a sonet frame into an ATM frame.
In order to properly prepare serial data for ATM, it is desirable to work with serial data as a differential clock or data signal pair having differential voltages ranging from approximately 100 mV to 1.2 V. Differential signal pairs offer the advantage of increased noise immunity. Usually BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) buffers are used to achieve a small differential voltage swing of high speed data or clock signals, with a differential clock or data signal pair known as PECL (Pseudo Emitter Common Logic) signals, but the costs associated with BiCMOS buffers at high frequencies are well known in the art. Using CMOS or NMOS technology as the alternative to BiCMOS buffers, a CMOS or NMOS differential amplifier may be directly connected to the differential clock or data signal pair. Unfortunately, a CMOS or NMOS process differential amplifier is often not fast enough at high frequencies, especially when input data are switching from an idle state to an active state at a high rate of speed. Therefore, there is an unmet need in the art to be able to compensate for the speed deficiency of a CMOS or NMOS differential amplifier at high frequencies.